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Freescale Semiconductor Product Brief
S12HFAMPP Rev. 11.1, 17-Aug-2004
16-bit Microcontroller HCS12H Family
Introduction
Designed for automotive instrumentation applications, all members of the MCS12H-Family of microcontroller units (MCU) are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, up to 4K bytes of EEPROM on Flash parts, one or two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ADC), up to six-channel pulse width modulator (PWM), and up to two CAN 2.0 A, B software compatible modules. In addition, they feature a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited to drive up to six stepper motors, and on selected devices, up to four stepper stall detectors (SSD) to simulataneously calibrate the pointer reset position of each motor. The MCS12H-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 14 I/O ports are available with Key-Wake-Up capability from STOP or WAIT mode.
(c) Freescale Semiconductor, Inc., 2004. All rights reserved. PRELIMINARY
Feature Detail
Feature Detail NOTE
Not all features listed here are available in all configurations. For a quick overview refer to Table 1. * HCS12 Core - HCS12 16-bit CPU
* Upward compatible with M68HC11 instruction set * Interrupt stacking and programmer's model identical to M68HC11 * Instruction queue * Enhanced indexed addressing
- - - - - *
HCS12 MEBI (Multiplexed Expanded Bus Interface) HCS12 MMC (Module Mapping Control) HCS12 INT (Interrupt Control) HCS12 BKP (On-chip Breakpoints) HCS12 BDM (Single-wire Background DebugTM Mode)
Memory options - 32K, 64K, 128K, 256K byte Flash EEPROM or 64K, 128K, 192K and 256K byte ROM - 2K, 4K, 6K, 8K, 12K byte RAM - 2K, 4K byte EEPROM on Flash versions only 8-bit and 4-bit ports with Interrupt capability - Digital filtering - Programmable rising or falling edge trigger Clock Reset Generator (CRG) - Low current Colpitts or Pierce oscillator (0.5 to 16Mhz reference clock) - Phase-locked loop clock frequency multiplier - Windowed COP watchdog and Clock Monitor resets - Real Time Interrupt Up to 16-channels Analog-to-Digital Converter (ADC) - 10-bit resolution - External conversion trigger capability Up to two 1M bit per second, CAN 2.0 A, B software compatible modules (MSCAN12) - Five receive and three transmit buffers - Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit - Four separate interrupt channels for Rx, Tx, error and wake-up - Low-pass filter wake-up function - Loop-back for self test operation Timer (TIM) - 16-bit main counter with 7-bit prescaler - Eight programmable input capture or output compare channels - Two 8-bit or one 16-bit pulse accumulators Up to six Pulse Width Modulator (PWM) channels
16-bit Microcontroller HCS12H Family, Rev. 11.1
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2 PRELIMINARY
Freescale Semiconductor
Feature Detail
- - - - - *
Programmable period and duty cycle for each channel Pairs of 8-bit channels can be concatenated as one 16-bit channel Center-aligned or left-aligned outputs Wide range of programmable clock frequencies Fast emergency shutdown input
Serial interfaces - Up to two asynchronous Serial Communications Interfaces (SCI) - Synchronous Serial Peripheral Interface (SPI) - Inter-IC Bus Interface (IIC) Liquid Crystal Display (LCD) driver - Up to 32 frontplanes and 4 backplanes - 5 modes of operation allow for different display sizes to meet application requirements - Programmable frame clock generator and bias voltage level 16 or 24 high current drivers suited for PWM motor control - Each PWM channel switchable between two drivers in an H-bridge configuration - Support for sine and cosine drive - 11-bit resolution with selectable dithering function - Left, right or center aligned outputs - Slew rate control Up to four Stepper Stall Detectors (SSD) - available on selected devices - Flexible full step and polarity set up to return the pointer to its reset position in clockwise or counter clockwise direction. - Integrator/Sigma Delta converter circuit to measure the induced voltage by the back EMF of unpowered coil during full step (only one of the two motor coils is powered) operation. - 16-Bit Down Counter to monitor blanking and integration time to support stepper motors with different gear ratios. - 16-Bit accumulator register to read integration value, compare to a threshold at the end of integration time, and decide if the motor is stalled under this value or moving above this value. Operating Frequency - 32Mhz equivalent to 16Mhz Bus Speed (Only 9S12H256) - 50Mhz equivalent to 25Mhz Bus Speed (Except 9S12H256) 80-Pin, 112-Pin or 144-Pin QFP package - I/O lines with 5V input and drive capability - 5V A/D converter inputs
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16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 3
Feature Detail
Table 1 List of MCS12H-Family members
Flash ROM RAM EEPROM 256K 256K 128K 256K 128K 64K 64K 64K 64K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 256K 192K 128K 128K 64K 64K 32K 32K 12K 12K 6K 12K 6K 4K 4K 4K 4K 12K 8K 6K 6K 4K 4K 2K 2K 4K 4K 2K 2K 2K 1K 1K 1K 1K 0 0 0 0 0 0 0 0 Device 9S12H256 9S12H256(1) 9S12HZ256 9S12HZ128 9S12HZ64 9S12HN64 9S12HZ64 9S12HN64 3S12HZ256 3S12HZ192 3S12HZ128 3S12HN128 3S12HZ64 3S12HN64 3S12HZ32 3S12HN32 Package 144 LQFP 112 LQFP CAN SCI SPI IIC A/D PWM TIM LCD Motor SSD KWU I/O 2 2 2 2 2 1 0 1 0 2 2 1 0 1 0 1 0 2 1 1 2 2 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 16 8 8 16 16 8 8 7 7 16 16 8 8 8 8 7 7 6 2 2 6 6 4 4 4 4 6 6 6 6 4 4 4 4 8 8 8 8 8 8 8 4 4 8 8 8 8 8 8 4 4 32x4 28x4 28x4 32x4 32x4 24x4 24x4 20x4 20x4 32x4 32x4 32x4 32x4 24x4 24x4 20x4 20x4 24/6 24/6 24/6 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 0 0 0 4 4 2 2 2 2 4 4 4 4 2 2 2 2 12 0 0 8 8 8 8 7 7 8 8 8 8 8 8 7 7 117 85 85 85 85 69 69 60 60 85 85 85 85 69 69 60 60
9S12H128(1) 112 LQFP 112 LQFP 112 LQFP 112 LQFP 112 LQFP 80 QFP 80 QFP 112 LQFP 112 LQFP 112 LQFP 112 LQFP 112 LQFP 112 LQFP 80 QFP 80 QFP
NOTES:
1. Not recommended for new designs.
*
Flash emulation of ROM versions - ROM versions 3S12HZ256, 3S12HZ192, 3S12HZ128 and 3S12HN128 should use the 9S12HZ256 for Flash emulation. - ROM versions 3S12HZ64, 3S12HN64, 3S12HZ32 and 3S12HN32 should use the 9S12HZ64 for Flash emulation. Pin out explanations: - A/D is the number of A/D channels. - PWM is the number of TIM channels. - LCD denotes the number of front planes times the number of back planes. - Motor denotes the number of high current drive pins / number of stepper motors which can be driven - SSD denotes whether this device features a Stepper Stall Detection Circuit - Versions with one SCI will use SCI0 - Versions with one CAN will use CAN0 - I/O is the sum of ports capable to act as digital input or output. 144 Pin Package: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 5, L = 8, M = 6, P = 6, S = 8, T = 8, U = 8, V = 8, W = 8, PAD = 16 input only. 14 inputs provide Interrupt capability (H = 8, J = 4, IRQ, XIRQ). 112 Pin Package for H Versions: Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 4, M = 4, P = 2, S = 6, T = 8, U = 8, V = 8, W = 8, PAD = 8 input only.
16-bit Microcontroller HCS12H Family, Rev. 11.1
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4 PRELIMINARY
Freescale Semiconductor
Feature Detail
2 inputs provide Interrupt capability (IRQ, XIRQ). 112 Pin Package for 9HZ256, 9HZ128, 3HZ128 and 3HN128 Versions: Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 8, M = 5, P = 6, S = 6, T = 8, U = 8, V = 8, PAD = 8. 10 inputs provide Interrupt capability (AD = 8, IRQ, XIRQ). 112 Pin Package for 9HZ64, 9HN64, 3HZ64 and 3HN64 Versions: Port A = 8, B = 4, E = 4 + 1 input only, K = 5, L = 4, M = 2, P = 4, S = 5, T = 8, U = 8, V = 8, PAD = 8. 9 inputs provide Interrupt capability (AD = 8, XIRQ). 80 Pin Package for 9HZ64, 9HN64, 3HZ32 and 3HN32 Versions: Port A = 8, B = 4, E = 4 + 1 input only, K = 5, M = 2, P = 4, S = 5, T = 4, U = 8, V = 8, PAD = 7. 8 inputs provide Interrupt capability (AD = 7, XIRQ). * Compatibility Considerations - Pins associated with Motors 0 and 5 should be left unconnected to ensure compatibility with versions featuring 4 Motors.
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 5
Block Diagram
Block Diagram
VDDR VDD1 VSS1,2
Voltage Regulator 128K, 256K Bytes Flash or ROM 2K, 4K Bytes EEPROM
6K, 12K Bytes RAM
VDDA VSSA VRH VRL AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 PW0 PW1 PW2 PW3 PW4 PW5 SDA SCL RXCAN0 TXCAN0 RXCAN1 TXCAN1 RXD0 TXD0 RXD1 TXD1 MISO MOSI SCK SS
VDDA VSSA VRH VRL PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PP0 PP1 PP2 PP3 PP4 PP5 PM0 PM1
CPU12 Periodic Interrupt COP Watchdog Clock Monitor
XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE4 PE5 PE6 VLCD XADDR14 XADDR15 XADDR16 XADDR17 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 PK0 PK1 PK2 PK3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE2 PE3 PE7 PK7
PLL
Clock and Reset Generation Module
Breakpoints
XIRQ IRQ ECLK MODA MODB VLCD BP0 BP1 BP2 BP3 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 IOC4 IOC5 IOC6 IOC7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 KWJ0 KWJ1 KWJ2 KWJ3
DDRP DDRM
DDRE
PTE
PIX0 PIX1 PIX2 PIX3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15
PPAGE
IIC CAN0 CAN1
DDRK
PTM
PTK
PTP
System Integration Module
Pulse Width Modulator
PTAD
BKGD
Single-Wire Background Debug Module
Analog to Digital Converter
PM2 PM3 PM4 PM5 PS0 PS1
DDRS PTS
LCD Driver
Multiplexed Address/Data Bus
DDRB
SCI0 SCI1 SPI
PTB
PS2 PS3 PS4 PS5 PS6 PS7 VDDM1 VSSM1 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 VDDM2 VSSM2 PV0 PV1
DDRA
MOTOR0 and MOTOR1 Supply
PWM0 MOTOR0 PWM1 PWM2 MOTOR1 PWM3 M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P
PTA
DDRU
DDRL
Multiplexed Multiplexed Narrow Wide Bus Bus
PTL
MOTOR2 and MOTOR3 Supply
PWM4 R/W LSTRB/TAGLO NOACC/XCLKS ECS/ROMCTL IOC0 IOC1 IOC2 IOC3 MOTOR2 PWM5 PWM6 MOTOR3 PWM7 M2C0M M2C0P
DDRV
DDRK
PTK
M3C0M M3C0P M3C1M M3C1P
PTV
Pins shown in BOLD are not available in the 112 QFP
DDRE
PTU
PTE
M2C1M M0C1P
PV2 PV3 PV4 PV5 PV6 PV7 VDDM3 VSSM2 PW0 PW1
MOTOR4 and MOTOR5 Supply
PWM8 MOTOR4 PWM9 PWM10 MOTOR5 PWM11 Supply pins M4C0M M4C0P
DDRW
Input Capture and Output Compare Timer
PTW
M4C1M M4C1P M5C0M M5C0P M5C1M M5C1P
PW2 PW3 PW4 PW5 PW6 PW7
Pin Interrupt Logic
A/D Converter 5V & Voltage Regulator Reference VDDA VSSA
I/O Driver 5V Internal Logic 2.5V VDD1 VDDX1,2 VSS1,2 VSSX1,2 PLL 2.5V VDDPLL VSSPLL Vreg Input 5V VDDR
Figure 1. MC9S12H-Family Block Diagram
16-bit Microcontroller HCS12H Family, Rev. 11.1 6 PRELIMINARY Freescale Semiconductor
Block Diagram
VDDR VDD1 VSS1,2
Voltage Regulator 256K, 128K Bytes Flash EEPROM or ROM 2K Bytes EEPROM 12K, 8K, 6K Bytes RAM
Analog to VSSA VRH Digital Converter VRL
AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 TXD1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
VDDA
VDDA1,2 VSSA1,2 VRH VRL KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 PW0 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PP0 PP1 PP2 PP3 PP4 PP5 PM2 PM3 PM4 PM5 PS0 PS1
DDRAD DDRP
DDRM
BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE4 PE5 PE6 VLCD XADDR14 XADDR15 XADDR16 XADDR17 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 PK0 PK1 PK2 PK3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE2 PE3 PE7 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7
Single-Wire Background Debug Module PLL Clock and Reset Generation Module
CPU12 Periodic Interrupt COP Watchdog Clock Monitor
RXD1
Breakpoints
IIC CAN0 CAN1 SCI0
SDA SCL
PW4 PW5
XIRQ IRQ ECLK MODA MODB VLCD BP0 BP1 BP2 BP3 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 IOC4 IOC5 IOC6 IOC7
DDRE
PTE
System Integration Module
RXCAN1 TXCAN1 RXD0 TXD0
PIX0 PIX1 PIX2 PIX3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
PPAGE
DDRK
PTK
DDRS PTS
PTM
RXCAN0 TXCAN0
PTP
SCI1
PW1 Pulse PW2 Width Modulator PW3
PTAD
SPI
Multiplexed Address/Data Bus
MISO MOSI SCK SS
PS4 PS5 PS6 PS7 VDDM1,2 VSSM1,2 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 VDDM2,3 VSSM2,3 PV0 PV1
DDRB
PTB
LCD Driver
MOTOR0 and MOTOR1 Supply
SSD0 M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP PWM0 PWM1 PWM2 PWM3 M0C0M M0C0P
DDRU
DDRA
PTA
SSD1
M1C0M M1C0P M1C1M M1C1P
MOTOR2 and MOTOR3 Supply
SSD2 M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP PWM4 PWM5 PWM6 PWM7 M2C0M M2C0P
DDRV
DDRL
Multiplexed Multiplexed Wide Narrow Bus Bus
SSD3
M3C0M M3C0P M3C1M M3C1P
PTV
PTL
M2C1M M2C1P
PTU
M0C1M M0C1P
PV2 PV3 PV4 PV5 PV6 PV7
R/W LSTRB/TAGLO NOACC/XCLKS ECS/ROMCTL IOC0 IOC1 IOC2 IOC3
DDRE
PTE
Supply pins A/D Converter 5V & Voltage Regulator Reference VDDA VSSA
DDRK
PTK
I/O Driver 5V Internal Logic 2.5V VDD1 VDDX1,2 VSS1,2 VSSX1,2 PLL 2.5V VDDPLL VSSPLL Vreg Input 5V VDDR
DDRT
PTT
Input Capture and Output Compare Timer
Figure 2. MC9S12H-Family "Z" Version Block Diagram
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 7
Pin Assignments
Pin Assignments
M0C0M/PU0 M0C0P/PU1 M0C1M/PU2 M0C1P/PU3 VDDM1 VSSM1 M1C0M/PU4 M1C0P/PU5 M1C1M/PU6 M1C1P/PU7 KWH0/PH0 KWH1/PH1 KWH2/PH2 KWH3/PH3 M2C0M/PV0 M2C0P/PV1 M2C1M/PV2 M2C1P/PV3 VDDM2 VSSM2 M3C0M/PV4 M3C0P/PV5 M3C1M/PV6 M3C1P/PV7 KWH4/PH4 KWH5/PH5 KWH6/PH6 KWH7/PH7 M4C0M/PW0 M4C0P/PW1 M4C1M/PW2 M4C1P/PW3 VDDM3 VSSM3 M5C0M/PW4 M5C0P/PW5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 PJ3/KWJ3 PJ2/KWJ2 PJ1/KWJ1 PJ0/KWJ0 VSSX1 VDDX1 PK7/ECS/ROMCTL/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL7/FP31 PL6/FP30 PL5/FP29 PL4/FP28 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
9S12H256 144 LQFP
Pins shown in BOLD are not available in the 112 QFP package
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD15/AN15 PAD7/AN7 PAD14/AN14 PAD6/AN6 PAD13/AN13 PAD5/AN5 PAD12/AN12 PAD4/AN4 PAD11/AN11 PAD3/AN3 PAD10/AN10 PAD2/AN2 PAD9/AN9 PAD1/AN1 PAD8/AN8 PAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
8 PRELIMINARY
M5C1M/PW6 M5C1P/PW7 PWM0/PP0 PWM1/PP1 PWM2/PP2 PWM3/PP3 PWM4/PP4 PWM5/PP5 RXD0/PS0 TXD0/PS1 RXD1/PS2 TXD1/PS3 VSS2 VDDR VDDX2 VSSX2 MODC/TAGHI/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SDA/PM0 SCL/PM1 RXCAN0/PM2 TXCAN0/PM3 RXCAN1PM4 TXCAN1/PM5 MODA/IPIPE0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Figure 1. 144-Pin Package Signal Assignments for 9S12H256
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor
Pin Assignments
M0C0M/PU0 M0C0P/PU1 M0C1M/PU2 M0C1P/PU3 VDDM1 VSSM1 M1C0M/PU4 M1C0P/PU5 M1C1M/PU6 M1C1P/PU7 M2C0M/PV0 M2C0P/PV1 M2C1M/PV2 M2C1P/PV3 VDDM2 VSSM2 M3C0M/PV4 M3C0P/PV5 M3C1M/PV6 M3C1P/PV7 M4C0M/PW0 M4C0P/PW1 M4C1M/PW2 M4C1P/PW3 VDDM3 VSSM3 M5C0M/PW4 M5C0P/PW5
M5C1M/PW6 M5C1P/PW7 PWM0/PP0 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2 MODC/TAGHI/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3
Figure 2. 112-Pin Package Signal Assignments for 9S12H256, 3S12H256 and 3S12H192
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 9
MODA/IPIPE0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
RXCAN1/PM4 TXCAN1/PM5
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/ECS/ROMCTL/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
9S12H256, 9S12H128, 3S12H256, 3S12H192 112 LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD7/AN7 PAD6/AN6 PAD5/AN5 PAD4/AN4 PAD3/AN3 PAD2/AN2 PAD1/AN1 PAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
Pin Assignments
FP28/AN12/PL4 FP29AN13//PL5 FP30/AN14//PL6 FP31/AN15/PL7 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 SCL/PWM5/PP5 SDA/PWM4/PP4
PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2 MODC/TAGHI/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3
RXCAN1/PM4 TXCAN1/PM5
Figure 3. 112-Pin Package Signal Assignments for 9S12HZ256, 9S12HZ128, 3S12HZ128 and 3S12HN128
16-bit Microcontroller HCS12H Family, Rev. 11.1 10 PRELIMINARY Freescale Semiconductor
MODA/IPIPE0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/ECS/ROMCTL/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
9S12HZ256, 9S12HZ128, 3S12HZ128, 3S12HN128 112 LQFP
Signals shown in BOLD are not available in the 80 QFP package
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
Pin Assignments
NC NC NC NC NC NC M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 NC NC PWM5/PP5 PWM4/PP4
PWM3/PP3 NC NC PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 NC VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3
Figure 4. 112-Pin Package Signal Assignments for 9S12HZ64, 9S12HN64, 3S12HZ64 and 3S12HN64
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 11
NC MISO/PS4 MOSI/PS5 SCK/PS6 NC NC
NC NC
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/FP23 PE7/XCLKS/FP22 PE3/FP21 PE2/FP20 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/FP15 PA6/FP14 PA5/FP13 PA4/FP12 PA3/FP11 PA2/FP10 PA1/FP9 PA0/FP8 PB7/FP7 PB6/FP6
9S12HZ64, 9S12HN64, 3S12HZ64, 3S12HN64 112 LQFP
Signals shown in BOLD are not available in the 80 QFP package
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/FP5 PB4/FP4 NC NC NC NC PK0/BP0 PK1/BP1 PK2/BP2 PK3/BP3 VLCD VSS1 VDD1 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA NC NC VSSA PE0/XIRQ PE4/ECLK NC
Pin Assignments
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/FP23 PE7/XCLKS/FP22 PE3/FP21 PE2/FP20 PA7/FP15 PA6/FP14 PA5/FP13 PA4/FP12 PA3/FP11 PA2/FP10 PA1/FP9 PA0/FP8 PB7/FP7 PB6/FP6 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 PWM5/PP5 PWM4/PP4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
9S12HZ64, 9S12HN64, 3S12HZ32, 3S12HN32 80 QFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PB5/FP5 PB4/FP4 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VSSA PE0/XIRQ PE4/ECLK
Figure 5. 80-Pin Package Signal Assignments for 9S12HZ64, 9S12HN64, 3S12HZ32 and 3S12HN32
12 PRELIMINARY
PWM3/PP3 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDX2 VSSX2 MODC/BKGD RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3 PS4 PS5 PS6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package. Note: Features shown in Italics are only available for the "Z" versions
Pin Name Pin Name Function 1 Function 2 EXTAL XTAL RESET TEST Pin Name Function 3 Pin Name Function 4 Description Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output Active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. Test Input Function 1: Pseudo-open-drain communication pin for the background debug function. Function 2: In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. Function 3: At the rising edge during reset, the state of this pin is latched to the MODC bit to set the MCU operating mode. Function 1: Port AD general purpose inputs Function 2: Analog inputs (ATD) Function 1: Port AD general purpose inputs Function 2: Analog inputs (ATD) Function 3: Key wake-up input pins that can generate an interrupt causing the MCU to exit STOP or WAIT mode. Function 1: Port A general purpose input or output pins. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. Function 1: Port B general purpose input or output pins. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. Function 1: Port E general purpose input or output pin Function 2: LCD frontplane segment driver output pin Function 3: The XCLKS signal selects between an external clock or oscillator configuration during reset. This pin should be at a logic high during reset if an external clock is used on the EXTAL input pin. This pin should be at a logic low during reset if an oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an oscillator circuit on EXTAL and XTAL. Function 4: During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus.

BKGD
TAGHI
MODC
PAD[15:8]
AN[15:8]
KWAD[7:0]

PAD[7:0]
AN[7:0]
PA[7:0]
FP[15:8]
ADDR[15:8]/D ATA[15:8]
PB[7:0]
FP[7:0]
ADDR[7:0]/DA TA[7:0]
PE7
FP22
XCLKS
NOACC
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 13
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package. Note: Features shown in Italics are only available for the "Z" versions
Pin Name Pin Name Function 1 Function 2 PE6 PE5 IPIPE1 IPIPE0 Pin Name Function 3 MODB MODA Pin Name Function 4 Description Function 1: Port E general purpose input or output pins. Function 2: Instruction queue tracking signals. Function 3: The state of the MODA and MODB pins during reset determine the initial operating mode of the MCU Function 1: Port E general purpose input or output pin. Function 2: Internal bus clock output that can be used as a timing reference. Function 1: Port E general purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operation, LSTRB is used for the low-byte strobe function to indicate the type of bus access. Function 4: When instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue. Function 1: Port E general purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: In MCU expanded modes of operations, performs the read/write output signal for the external bus. This pin indicates direction of data on the external bus. Function 1: Port E general purpose input pin. Function 2: Maskable interrupt request input provides a means of applying asynchronous interrupt requests. Will wake up the MCU from STOP or WAIT mode Function 1: Port E general purpose input pin. Function 2: Nonmaskable interrupt request input provides a means of applying asynchronous interrupt requests. Will wake up the MCU from STOP or WAIT mode. Function 1: Port H general purpose input or output pins. Function 2: Key wake-up input pins that can generate an interrupt causing the MCU to exit STOP or WAIT mode. Function 1: Port J general purpose input or output pins. Function 2: Key wake-up input pins that can generate an interrupt causing the MCU to exit STOP or WAIT mode. Function 1: Port K general purpose input or output pin. Function 2: LCD frontplane segment driver output pin. Function 3: During MCU expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map. Function 4: During MCU expanded modes of operation, this pin is used as the emulation chip select signal. Function 1: Port K general purpose input or output pins. Function 2: LCD backplane segment driver output pins. Function 3: In MCU expanded modes of operation, expanded address pins for the external bus. Function 1: Port L general purpose input or output pins. Function 2: LCD frontplane segment driver output pins. Function 3: Analog inputs (ATD).

PE4
ECLK
PE3
FP21
LSTRB
TAGLO
PE2
FP20
R/W
PE1
IRQ
PE0
XIRQ

PH[7:0]
KWH[7:0]
PJ[3:0]
KWJ[3:0]
PK7
FP23
ECS
ROMCTL
PK[3:0]
BP[3:0]
XADDR[17:14]

PL[7:4]
FP[31:28]
AN[15:12]
16-bit Microcontroller HCS12H Family, Rev. 11.1 14 PRELIMINARY Freescale Semiconductor
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package. Note: Features shown in Italics are only available for the "Z" versions
Pin Name Pin Name Function 1 Function 2 PL[3:0] FP[19:16] Pin Name Function 3 AN[11:08] Pin Name Function 4 Description Function 1: Port L general purpose input or output pins. Function 2: LCD frontplane segment driver output pins. Function 3: Analog inputs (ATD). Function 1: Port M general purpose input or output pin. Function 2: Transmit pin for the Motorola Scalable Controller Area Network controller 1 (MSCAN1). Function 1: Port M general purpose input or output pin. Function 2: Receive pin for the Motorola Scalable Controller Area Network controller 1 (MSCAN1). Function 1: Port M general purpose input or output pin. Function 2: Transmit pin for the Motorola Scalable Controller Area Network controller 0 (MSCAN0). Function 1: Port M general purpose input or output pin. Function 2: Receive pin for the Motorola Scalable Controller Area Network controller 0 (MSCAN0). Function 1: Port M general purpose input or output pin. Function 2: Serial clock pin for the Inter-IC Bus Interface (IIC). Function 1: Port M general purpose input or output pin. Function 2: Serial data pin for the Inter-IC Bus Interface (IIC). Function 1: Port P general purpose input or output pins. Function 2: Pulse Width Modulator (PWM) channel output pins. Function 3: Serial clock pin for the Inter-IC Bus Interface (IIC). Function 1: Port P general purpose input or output pins. Function 2: Pulse Width Modulator (PWM) channel output pins. Function 3: Serial data pin for the Inter-IC Bus Interface (IIC). Function 1: Port P general purpose input or output pins. Function 2: Pulse Width Modulator (PWM) channel output pins. Function 3: Transmit pin of Serial Communication Interface 1 (SCI1). Function 1: Port P general purpose input or output pins. Function 2: Pulse Width Modulator (PWM) channel output pins. Function 3: Receive pin of Serial Communication Interface 1 (SCI1). Function 1: General purpose input or output pin. Function 2: Pulse Width Modulator (PWM) channel output pin. Function 1: General purpose input or output pin. Function 2: Pulse Width Modulator (PWM) channel output pin. Function 3: Transmit pin of Serial Communication Interface 1 (SCI1).

PM5
TXCAN1

PM4
RXCAN1
PM3
TXCAN0
PM2
RXCAN0
PM1
SCL
PM0
SDA
PP5
PWM5
SCL
PP4
PWM4
SDA
PP3
PWM3
PP2
PWM2
RXD1

PP1
PWM1
TXD1
PP0
PWM0
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 15
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package. Note: Features shown in Italics are only available for the "Z" versions
Pin Name Pin Name Function 1 Function 2 PS7 SS Pin Name Function 3 Pin Name Function 4 Description Function 1: Port S general purpose input or output pin. Function 2: Slave select pin for the Serial Peripheral Interface (SPI). Function 1: Port S general purpose input or output pin. Function 2: Serial clock pin for the Serial Peripheral Interface (SPI). Function 1: Port S general purpose input or output pin. Function 2: Master output (during master mode) or slave input (during slave mode) pin for the Serial Peripheral Interface (SPI). Function 1: Port S general purpose input or output pin. Function 2: Master input (during master mode) or slave output (during slave mode) pin for the Serial Peripheral Interface (SPI). Function 1: Port S general purpose input or output pin. Function 2: Transmit pin of Serial Communication Interface 1 (SCI1). Function 1: Port S general purpose input or output pin. Function 2: Receive pin of Serial Communication Interface 1 (SCI1). Function 1: Port S general purpose input or output pin. Function 2: Transmit pin of Serial Communication Interface 0 (SCI0). Function 1: Port S general purpose input or output pin. Function 2: Receive pin of Serial Communication Interface 0 (SCI0). Function 1: Port T general purpose input or output pins. Function 2: Timer input capture or output compare pins. Function 1: Port T general purpose input or output pins. Function 2: Timer input capture or output compare pins. Function 3: LCD frontplane segment driver output pins. Function 1: Port U general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high state. Function 1: Port U general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. Function 1: Port U general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state.

PS6
SCK
PS5
MOSI
PS4
MISO

FP[27:24]

PS3
TXD1
PS2
RXD1
PS1
TXD0
PS0 PT[7:4] PT[3:0] PU7 PU6 PU5 PU4 PU3 PU2
RXD1 IOC[7:4] IOC[3:0] M1C1P M1C1M M1C0P M1C0M M0C1P M0C1M

16-bit Microcontroller HCS12H Family, Rev. 11.1 16 PRELIMINARY Freescale Semiconductor
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package. Note: Features shown in Italics are only available for the "Z" versions
Pin Name Pin Name Function 1 Function 2 PU1 PU0 PV7 PV6 PV5 PV4 PV3 PV2 PV1 PV0 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 M0C0P M0C0M M3C1P M3C1M M3C0P M3C0M M2C1P M2C1M M2C0P M2C0M M5C1P M5C1M M3C0P M5C0M M4C1P M4C1M M4C0P M4C0M Pin Name Function 3 Pin Name Function 4 Description Function 1: Port U general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. Function 1: Port V general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state. Function 1: Port V general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. Function 1: Port V general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state. Function 1: Port V general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven to a logic high state. Function 1: Port W general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on M5C1M results in a positive current flow through coil 1 when M5C1P is driven to a logic high state. Function 1: Port W general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 5. PWM output on M5C0M results in a positive current flow through coil 0 when M5C0P is driven to a logic high state. Function 1: Port W general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on M4C1M results in a positive current flow through coil 1 when M4C1P is driven to a logic high state. Function 1: Port W general purpose input or output pins. Function 2: High current PWM output pins which can be used for motor drive. These pins interface to the coils of motor 4. PWM output on M4C0M results in a positive current flow through coil 0 when M4C0P is driven to a logic high state. Supply input pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast.

VLCD
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 17
Pin Assignments
Table 2 Pin Descriptions
Note: Features shown in bold are not available in the 9S12H256 112 pin QFP package. Note: Features shown in Italics are only available for the "Z" versions
Pin Name Pin Name Function 1 Function 2 VDDA VSSA VRH VRL VDDM1 VSSM1 VDDM2 VSSM2 VDDM3 VSSM3 VDDPLL VSSPLL VDDX1 VSSX1 VDDX2 VSSX2 VDD1 VSS1 VSS2 VDDR Pin Name Function 3 Pin Name Function 4 Description Supply input pins for the voltage regulator and the analog to digital converter. Tolerance = 5V 5%. Reference voltage input pins for the analog to digital converter. Supply input pins for motor 0 and motor 1 output drivers. Tolerance = 5 V 10%. Supply input pins for motor 2 and motor 3 output drivers. Tolerance = 5 V 10%. Supply input pins for motor 4 and motor 5 output drivers. Tolerance = 5 V 10%. PLL supply output pins. No load allowed except for bypass capacitors.

Supply input pins for input/output drivers. Tolerance = 5V 5%.
Core supply output pins. No load allowed except for bypass capacitors. Power supply input pin for voltage regulator. Nominal 5V
16-bit Microcontroller HCS12H Family, Rev. 11.1 18 PRELIMINARY Freescale Semiconductor
Memory Maps
Memory Maps
$0000 $0000 $0400 $1000 $03FF $0000 $0FFF $1000
1K Register Space Mappable to any 2K Boundary 4K Bytes EEPROM Initially overlapped by register space Mappable to any 4K Boundary 12K Bytes RAM Alignable to top ($1000 - $3FFF) or bottom ($0000 - $2FFF)
$4000
$3FFF $4000
Mappable to any 16K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $1000 - $3FFF: 12K RAM for MC9S12H256 $0000 - $0FFF: 4K EEPROM (1K not visible) on MC9S12H256 only. There is no mapping of EEPROM Flash on MC3S12H256.
Figure 6. MC9(3)S12H256 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 19
Memory Maps
$0000 $0000 $0400 $0800 $1000 $03FF $0800 $0FFF $1000 $3FFF $4000
1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 12K Bytes RAM Mappable to any16K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Sixteen * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $1000 - $3FFF: 12K RAM $0000 - $07FF: 2K EEPROM (1K not visible) There is no mapping of EEPROM Flash on MC3S12HZ256.
Figure 7. MC9(3)S12HZ256 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1 20 PRELIMINARY Freescale Semiconductor
Memory Maps
$0000 $0000 $0400 $03FF
1K Register Space Mappable to any 2K Boundary
$2000
$2000 $3FFF $4000
8K Bytes RAM Mappable to any 8K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Twelve * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM (1K not visible)
Figure 8. MC3S12HZ192 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 21
Memory Maps
$0000 $0000 $0400 $0800 $1000 $2800 $03FF $0800 $0FFF $2800 $3FFF $4000
1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 6K Bytes RAM Alignable to top ($2800 - $3FFF) or bottom ($2000 - $37FF) of 8K Boundary Mappable to any 8K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Eight * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $1FFF: 6K RAM $0000 - $07FF: 2K EEPROM (1K not visible) There is no mapping of EEPROM Flash on MC3S12HZ(N)128.
Figure 9. MC9(3)S12HZ(N)128 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1 22 PRELIMINARY Freescale Semiconductor
Memory Maps
$0000 $0000 $0400 $0800 $1000 $3000 $03FF $0800 $0FFF $3000 $3FFF $4000
1K Register Space Mappable to any 2K Boundary 1K Bytes EEPROM (1K mapped twice in 2K Boundary) Mappable to any 2K Boundary 4K Bytes RAM Mappable to any 4K Boundary 0.5K, 1K, 2K or 4K Protected Sector
$4000
$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Four * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (1K not visible) $0000 - $07FF: 1K EEPROM mapped twice (not visible) There is no mapping of EEPROM Flash on MC3S12HZ(N)64
Figure 10. MC9(3)S12HZ(N)64 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 23
Memory Maps
$0000 $0000 $0400 $0800 $1000 $03FF $0800 $0FFF
1K Register Space Mappable to any 2K Boundary 2K Bytes RAM Mappable to any 2K Boundary
$8000 $8000 EXT $BFFF $C000 $C000 16K Fixed Flash EEPROM 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM
Figure 11. MC3S12HZ(N)32 User Configurable Memory Map
16-bit Microcontroller HCS12H Family, Rev. 11.1 24 PRELIMINARY Freescale Semiconductor
Mechanical Package Dimensions
Mechanical Package Dimensions
0.20 T L-M N 0.20 T L-M N
4X
4X 36 TIPS
PIN 1 IDENT 1
144
109
108
J1 L M B V
140X
4X
P
J1 C L X G
VIEW Y
36 37 72 73
B1
V1
VIEW Y
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE
MILLIMETERS DIM MIN MAX A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 0 1 0 7 2 11 13
N A1 S1 A S
VIEW AB C 2 2 T 0.1 T
144X
SEATING PLANE
PLATING
J
F
AA
C2 0.05 R2 R1
D 0.08
M
BASE METAL
0.25
GAGE PLANE
T L-M N (K) C1 (Y) VIEW AB E (Z)
SECTION J1-J1 (ROTATED 90 )
144 PL
1
Figure 3. 144-pin LQFP Mechanical Dimensions (case no. 918-03)
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 25
Mechanical Package Dimensions
4X PIN 1 IDENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M V
B1
V1
J
AA
28 29 56
57
F D 0.13
M
BASE METAL
N A1 S1 A S
T L-M N
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --- 1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
3 T
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
R
R2 R1 0.25
GAGE PLANE
R
C1 (Y) VIEW AB (Z)
(K) E
1
Figure 4. 112-pin LQFP Mechanical Dimensions (case no. 987)
16-bit Microcontroller HCS12H Family, Rev. 11.1 26 PRELIMINARY Freescale Semiconductor
Mechanical Package Dimensions
L
60 61 41 40
S
S
B B P
D
L
0.20 M H A-B
B
V 0.05 D
0.20 M C A-B
-A-
-B-
S
S
D
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-DA 0.20 M H A-B 0.05 A-B S 0.20 M C A-B
S S
F
D
S
J D
S
N
E C -CSEATING PLANE
M
DETAIL C -HDATUM PLANE
D 0.20 M C A-B
S
D
S
SECTION B-B
H G
0.10 M
VIEW ROTATED 90
U T
DATUM -HPLANE
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure 5. 80-pin QFP Mechanical Dimensions (case no. 841B)
16-bit Microcontroller HCS12H Family, Rev. 11.1 Freescale Semiconductor PRELIMINARY 27
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S12HFAMPP Rev. 11.1, 17-Aug-2004
PRELIMINARY

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